1. Field of the Invention
The present invention relates to a semiconductor device, and especially to a technique for independently controlling the threshold voltages of a plurality of MIS (metal insulator semiconductor) field-effect transistors (hereinafter referred to as xe2x80x9cMISFETsxe2x80x9d) comprised in a semiconductor device.
2. Description of the Background Art
FIG. 9 illustrates a schematic cross-sectional view of a conventional semiconductor device 1P. The semiconductor device 1P is a basic CMOS (complementary MOS) device comprising both an n-channel MOS (metal oxide semiconductor) field-effect transistor (hereinafter referred to as an xe2x80x9cnMOSFETxe2x80x9d) 10P and a p-channel MOSFET (hereinafter referred to as a xe2x80x9cpMOSFETxe2x80x9d) 30P. Such a semiconductor device 1P is disclosed for example in Japanese Patent Application Laid-open No. 6-61437 (1994), FIG. 6.
As shown in FIG. 9, a semiconductor substrate 2P is divided into active regions by an isolation oxide film 3P. A p-well 11P for the nMOSFET 10P is formed in one of the active regions of the semiconductor substrate 2P, whereas an n-well 31P for the pMOSFET 30P is formed in another active region adjacent to the above one.
In the surface of the p-well 11P, a pair of n-type impurity layers 12P and 13P are formed with a channel region sandwiched in between. A gate insulating film 14P composed of a silicon oxide film such as a thermal oxide film is formed on the channel region in the p-well 11P and a gate electrode 15P is formed on the gate insulating film 14P.
Similarly, in the surface of the n-well 31P, a pair of p-type impurity layers 32P and 33P are formed with a channel region sandwiched in between. A gate insulating film 34P composed of a silicon oxide film such as a thermal oxide film is formed on the channel region in the n-well 31P and a gate electrode 35P is formed on the gate insulating film 34P.
For low resistance, the gate electrodes 15P and 35P are doped with impurities such as phosphorus or boron by ion implantation or the like.
An interlayer insulation film 4P is formed over the whole surface of the semiconductor substrate 2P to cover the gate electrodes 15P and 35P. The interlayer insulation film 4P has formed therein contact holes which connect the impurity layers 12P, 13P, 32P, and 33P to wires 17P, 18P, 37P, and 38P, respectively.
For example when the gate electrodes 15P and 35P are doped with phosphorus, due to (the presence or absence of) the work function difference between the gate electrodes 15P, 35P and their opposing channel regions, the following operating discrepancy arises between the nMOSFET 10P and the pMOSFET 30P.
In the nMOSFET 10P, since the gate electrode 15P is formed on the p-well 11P, a positive work function difference xcex94"PHgr"ƒ with respect to the p-well 11P (or the substrate 2P) arises between the gate electrode 15P and the p-well 11P. Accordingly, the energy band in the vicinity of the channel bends downwardly when the potential of the gate electrode 15P is equal to the substrate potential. From this, an inversion layer can be formed by slightly applying a positive potential to the gate electrode 15P.
In the pMOSFET 30P, on the other hand, since the gate electrode 35P is formed on the n-well 31P, no work function difference with respect to the substrate 2P arises between the phosphorus-doped n-type gate electrode 35P and the n-well 31P. Thus, the energy band in the vicinity of the channel is almost flat when the potential of the gate electrode 35P is equal to the substrate potential. From this, for formation of an inversion layer in the pMOSFET 30P, the gate electrode 35P must be set at a fairly high negative potential. That is, the threshold voltage (hereinafter also referred to as a xe2x80x9cthreshold valuexe2x80x9d) is increased.
When both the gate electrodes 15P and 35P are doped with the same type of impurity, the threshold voltages of the nMOSFET 10P and the pMOSFET 30P are determined by the work function differences between the gate electrodes 15P, 35P and their opposing channel regions. That is, the conventional semiconductor device 1P has difficulty in controlling the threshold values of the nMOSFET 10P and the p-MOSFET 30P to the proper values.
As a measure to resolve such a problem, there is a method for independently controlling the threshold values of the MOSFETs 10P and 30P by doping the gate electrode 15P of the nMOSFET 10P with phosphorus and doping the gate electrode 35P of the pMOSFET 30P with boron.
The boron implanted in the gate electrode 35P will, however, diffuse (penetrate) into the channel region in a subsequent thermal treatment process and therefore it may cause problems such as an unintentional threshold-voltage increase. In next-generation MOSFETs, since a thin silicon oxide film of about 2 nm or less is used for the gate insulating film 34P, the above boron penetration is more likely to occur and thus changes in MOSFET characteristics are taken as an important issue.
Other examples of the methods for independently controlling the threshold values of the MOSFETs 10P and 30P include adjustment of the amount of dopant in the channel region and doping of the channel region with a counter impurity. However, such methods cause a considerable change in the impurity concentration of the channel region, resulting in characteristic deterioration such as an increase in channel leakage. Therefore, it is difficult to accomplish a dramatic threshold voltage shift, and the like.
In a system LSI, for specifications reasons, MOSFETs for logic circuit, MOSFETs for memory cell, and MOSFETs for I/O circuit often have different threshold voltages. In such a case, also, the aforementioned difficulty in controlling the threshold voltages becomes an issue.
A first aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate; a first MISFET including a first gate insulating film formed on the semiconductor substrate; and a second MISFET including a second gate insulating film formed on the semiconductor substrate, wherein the first gate insulating film includes, at least in part, a first dielectric film containing first metal ions and having a relative dielectric constant of 8 or more, the second gate insulating film includes, at least in part, a second dielectric film containing second metal ions and having a relative dielectric constant of 8 or more, first doping is performed on the first dielectric film using at least one kind of first impurity metal ions whose valence number differs by 1 from that of the first metal ions, and/or second doping is performed on the second dielectric film using at least one kind of second impurity metal ions whose valence number differs by 1 from that of the second metal ions, and wherein due to the first and/or second doping, at least one of the density and polarity of charged defects differs between the first dielectric film and the second dielectric film.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the first dielectric film and the second dielectric film are made of the same material.
According to a third aspect of the present invention, in the semiconductor device of the second aspect, the first MISFET includes an n-channel MISFET, the second MISFET includes a p-channel MISFET, the at least one kind of first impurity metal ions includes third metal ions having a valence number greater than the first metal ions, the at least one kind of second impurity metal ions includes fourth metal ions having a valence number greater than the second metal ions, and when the first doping and the second doping are both performed, a concentration of the third metal ions is set to be not less than that of the fourth metal ions.
According to a fourth aspect of the present invention, in the semiconductor device of either the second or the third aspect, the first MISFET includes an n-channel MISFET, the second MISFET includes a p-channel MISFET, the at least one kind of first impurity metal ions includes fifth metal ions having a valence number smaller than the first metal ions, the at least one kind of second impurity metal ions includes sixth metal ions having a valence number smaller than the second metal ions, and when the first doping and the second doping are both performed, a concentration of the fifth metal ions is set to be not more than that of the sixth metal ions.
According to a fifth aspect of the present invention, in the semiconductor device of the second aspect, the first and second MISFETs include MISFETs of the same channel type, the at least one kind of first impurity metal ions includes third metal ions having a valence number greater than the first metal ions, the at least one kind of second impurity metal ions includes fourth metal ions having a valence number greater than the second metal ions, and when the first doping and the second doping are both performed, a concentration of the third metal ions is set to be not less than that of the fourth metal ions.
According to a sixth aspect of the present invention, in the semiconductor device of either of the second through fifth aspects, the first and second MISFETs include MISFETs of the same channel type, the at least one kind of first impurity metal ions includes fifth metal ions having a valence number smaller than the first metal ions, the at least one kind of second impurity metal ions includes sixth metal ions having a valence number smaller than the second metal ions, and when the first doping and the second doping are both performed, a concentration of the fifth metal ions is set to be not more than that of the sixth metal ions.
According to a seventh aspect of the present invention, in the semiconductor device of either of the first through sixth aspects, materials of the first and second dielectric films each include at least one of Al2O3, Y2O3, and La2O3, and the at least one kind of first impurity ions and the at least one kind of second impurity ions each include at least one of bivalent ions including Ba, Sr, Mg and Ca ions, and quadrivalent ions including Ti, Zr, Hf, Si, and Pr ions.
According to an eighth aspect of the present invention, in the semiconductor device of either of the first through sixth aspects, materials of the first and second dielectric films each include at least one of TiO2, ZrO2, HfO2, and PrO2, and the at least one kind of first impurity metal ions and the at least one kind of second impurity metal ions each include at least one of trivalent ions including Al, Y and La ions, and quinquevalent ions including Ta and Nb ions.
According to a ninth aspect of the present invention, in the semiconductor device of either of the first through eighth aspects, a dopant concentration of the at least one kind of first and/or second impurity metal ions is in the range of 0.1 atomic % to 10 atomic %.
A tenth aspect of the present invention is directed to a method of manufacturing the semiconductor device of either of the first through ninth aspects, the method comprising the steps of: (a) preparing the semiconductor substrate; and (b) forming the first and second dielectric films, wherein the step (b) includes the step of: (b-1) performing first and/or second doping by using at least one of a MOCVD and an ion implantation methods.
According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the tenth aspect, the first and/or second doping is performed by the MOCVD method, and an organic metal used as a supply source of the at least one kind of first impurity metal ions and/or the at least one kind of second impurity metal ions contains a common organic ligand with an organic metal used as a supply source of the first and/or second metal ions.
A twelfth aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate; a first MISFET including a first gate insulating film formed on the semiconductor substrate; and a second MISFET including a second gate insulating film formed on the semiconductor substrate, wherein the first gate insulating film includes, at least in part, a first dielectric film containing predetermined metal ions and having a relative dielectric constant of 8 or more, the second gate insulating film includes, at least in part, a second dielectric film, doping is performed on the first dielectric film using at least one kind of impurity metal ions whose valence number differs by 1 from that of the predetermined metal ions, and wherein a threshold voltage difference between the first MISFET and the second MISFET is accomplished by controlling at least one of the density and polarity of charged defects caused by the doping in the first dielectric film.
According to the first aspect of the present invention, since the density and/or polarity of charged defects due to doping differs between the first and second dielectric films, the first and second dielectric films can be in different charged states. Thus, even if the gate electrodes of the first and second MISFETs are made of the same material, it is possible to independently control the state of the energy band of the semiconductor substrate in the vicinity of the first gate insulating film and the same in the vicinity of the second insulating film. Accordingly, the threshold voltages of the first and second MISFETs can be controlled independently. At this time, in the semiconductor device, boron penetration in the gate electrodes (of polycrystalline silicon) and channel leakage due to doping of the channel regions of the MISFETs are suppressed, as compared with those in conventional semiconductor devices. Therefore, as compared with conventional semiconductor devices, the semiconductor device can control the threshold voltage of the first MISFET over a wider voltage range with greater accuracy (while inhibiting unintentional threshold voltage shifts).
According to the second aspect of the present invention, the semiconductor device can be manufacture more simply than would be possible if the first and second dielectric films are made of different materials.
According to the third aspect of the present invention, when the n-channel and p-channel MISFETs constitute a CMOS, for example, consistency can be achieved between the threshold values of both the MISFETs. In addition, the threshold voltage of the n-channel MISFET can be reduced.
According to the fourth aspect of the present invention, when the n-channel and p-channel MISFETs constitute a CMOS, for example, consistency can be achieved between the threshold values of both the MISFETs. In addition, the threshold voltage of the p-channel MISFET can be reduced.
According to the fifth aspect of the present invention, the first and second MISFETs of the same channel type can have different threshold voltages. This enables the provision of a semiconductor device which comprises, for example, both MISFETs for logic circuit having a low threshold voltage and MISFETs for I/O circuit having a high threshold voltage.
According to the sixth aspect of the present invention, the first and second MISFETs of the same channel type can have different threshold voltages. This enables the provision of a semiconductor device which comprises, for example, both MISFETs for logic circuit having a low threshold voltage and MISFETs for I/O circuit having a high threshold voltage.
According to the seventh aspect of the present invention, a semiconductor device can be provided which is capable of independently controlling the threshold voltages of the first and second MISFETs.
According to the eighth aspect of the present invention, a semiconductor device can be provided which is capable of independently controlling the threshold voltages of the first and second MISFETs.
According to the ninth aspect of the present invention, charged defects can be generated which can considerably vary the threshold voltages of the MISFETs.
According to the tenth aspect of the present invention, a good-quality, impurity-doped first and/or dielectric film can be formed.
According to the eleventh aspect of the present invention, a side reaction between the ligands of the organic metals can be inhibited, which allows film formation with a high degree of reproducibility.
According to the twelfth aspect of the present invention, a difference in threshold voltage can be produced between the first and second MISFETs by controlling at least one of the density and polarity of charged defects due to doping of the first dielectric film. At this time, the threshold voltage difference between the first and second MISFETs can be easily produced by controlling the density and/or polarity of charged defects in the first dielectric film. Also, in the semiconductor device, boron penetration in the gate electrodes (of polycrystalline silicon) and channel leakage due to doping of the channel regions of the MISFETs are suppressed, as compared with those in conventional semiconductor devices. Therefore, as compared with conventional semiconductor devices, the semiconductor device can control the threshold voltage of the first MISFET over a wider voltage range with greater accuracy (while inhibiting unintentional threshold voltage shifts).
An object of the present invention is to provide a semiconductor device which comprises a plurality of MISFETs each having an independently controlled threshold voltage.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.